(a) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a structure suited for a static random access memory (DRAM) device.
(b) Description of the Related Art
In a SRAM device, write and read operations for memory cells are generally performed through a pair of digit lines (bit lines), which requests that two metallic digit lines be disposed between adjacent two columns of the memory cells. With the advance of a finer pattern in the memory array, the space between adjacent two metallic lines has been reduced and the parasitic capacitance of the gate electrode has increased. This means that the speed of the potential change of the digit lines does not increase to the extent that the pattern dimensions of the memory array decrease.
To increase the operational speed of the SRAM device, Patent Publication JP-A-4-335296 proposes a technique wherein each of the pair of digit lines is shared by adjacent two columns of the memory cells. FIG. 1 shows the proposed SRAM device, wherein only one of the rows and four of the columns in n.times.m matrix are shown in the drawing for brevity.
Each memory cell 11, 12, . . . 1 m in has a flip-flop for storing data on a pair of internal memory nodes and a pair of transfer transistors controlled by a corresponding one of word lines W1 and W2 for connecting the memory nodes in a selected memory cell to the pair of digit lines disposed adjacent thereto. Specifically, memory cells 11 and 13 each disposed in an odd-numbered column is connected to digit lines B1 and B2 and digit lines B3 and B4, respectively, and word line W1. Memory cells 12 and 14 each disposed in an even-numbered column is connected to digit lines B2 and B3 and digit lines B4 and B5, respectively, and word line W2.
Signals for activating the word lines W1 and W2 are generated by respective word drivers WD1 and WD2 implemented by AND gates receiving at inputs thereof a signal (word decoded signal) X1 from a row decoder not shown and bank selection signals BS1 and BS2, which specify an odd-numbered bank and an even-numbered bank, respectively. The data on the selected pair of digit lines B1-Bm+1 is transferred to data lines D and DB through a corresponding pair of column switches (implemented by transfer gates) each including an nMOSFET (such as M1a, M1b) and a pMOSFET (such as M2a, M2b) having gates for receiving a pair of digit line selection signals Y1 and Y1B, Y2 and Y2B, . . . . The digit line selection signals are generated by an AND of a signal from a column decoder and bank selection signal BS1 or BS2.
In operation, when a memory cell in an odd-numbered column, memory cell 11 for example, is to be selected, word line W1 and digit line selection signals Y1 and Y1B are activated by word, digit and bank selection signals to couple the digit lines B1 and B2 to data lines D and DB, respectively. As a result, the data read out from memory cell 11 in a read operation generates a potential difference between the digit lines B1 and B2 and is transferred to the data lines D and DB, whereas data supplied from the data lines D and DB in a write operation is transferred to and stored in memory cell 11 through the digit lines B1 and B2.
When a memory cell in an even-numbered row, memory cell 12 for example, is to be selected subsequently, word line W2 and digit line selection signals Y2 and Y2B are activated to couple memory cell 11 to the digit lines B2 and B3 and couple the digit lines B2 and B3 to the data lines D and DB after the bank selection signal is changed. In this exemplified operation, digit line B2 is common to memory cell 11 and memory cell 12, and a similar situation results in the memory cells in each adjacent two of the columns.
The configuration of a single digit line for each adjacent two of the columns as described above has the advantages of a larger space between digit lines, reduction of parasitic capacitance between the digit lines, improved yield (ratio of the number of non-defective products to the number of total products) due to a lower possibility of a short-circuit failure and space reduction of memory cells due to a lower limit for the line space over the conventional SRAM device.
The proposed SRAM device, however, has problems when implemented as a practical product. Specifically, the signal lines transmitting the digit line selection signals Y1 and Y1B and the pair of transfer gates such as M1a, M1b, M2a and M2b disposed for each of the columns substantially define the pitch of the columns in the product, which fact prevents the reduction of the space between the memory cells. In addition, a pair of word drives disposed for each of the rows in the peripheral circuit of the SRAM device substantially define the pitch of the rows of the memory cell. Further, the region for receiving high-density interconnects for the transfer gates tends to reduce the yield due to the requested finer pattern for the high-density interconnects. In short, it is generally difficult to obtain the advantages from the reduction of the digit lines in number without further improving the layout of the peripheral circuit of the SRAM device.
Another configuration which improves the line density for the digit line selection circuit is proposed in Patent Publication JP-A-7-21780 (second publication). FIG. 2 shows a block diagram of the proposed SRAM, wherein the number of transfer gates is reduced down to substantially a half the number of the transfer gates in the aforementioned (first) publication. A digit line B1, B2, B3 . . . is associated only with a pair of transistors such as nMOSFET 31a and pMOSFET 32a in the second publication. In FIGS. 1 and 2, similar constituent elements are designated by the same or similar reference numerals for the sake of understanding.
In FIG. 2, when memory cell 11 is to be selected, signals Y1B and Y2B are low and high, respectively, resulting in ON-state of nMOSFETs M31a, M31b and M31c and pMOSFETs M32a, M32b and M32c. As a result, three digit lines B1, B2 and B3 are coupled to data line D or DB, which may involve erroneous read-out of the data from memory cell 13 or erroneous storing of the data on the data line D and DB in memory cell 13 due to the active state of word line W1 although such a erroneous read-out or storing from memory cell 12 is prevented by an inactive state of word line W2.